In systems employing multiple clock signals, it is often necessary to be able to detect when two clocks bear a certain phase relationship, i.e. a certain phase-alignment with respect to one another. There are well known techniques in the art for accomplishing this, and these techniques usually provide a high-degree of accuracy. However, such techniques typically involve sophisticated hardware.
Sometimes, phase-alignment, or the detection of phase-alignment, between two different clock clocks signals may be required after a system has been implemented. In such situations, it is too late for an integrated hardware solution, although one could possibly incorporate external circuitry to detect clock-signal alignment according to known methods. This is undesirable from an integration and robustness point of view, and furthermore increases the cost of a system.
In Global Navigation Satellite System (GNSS) timing products, the precise synchronisation capability of a GNSS receiver is used to generate a timing signal which can be used in timing applications. This signal may be a ‘Pulse per Second’ (PPS) signal which, as the name implies, is a 1 Hz signal that is output by the GNSS receiver and is synchronized to UTC second rollover via transmissions received from GNSS satellites. Alternatively, it is known to use a 1 kHz signal or an ‘Even Second’ signal (which is 0.5 Hz but specifically uses evenly numbered seconds).
This pulse by itself is usually not enough to synchronize user equipment. The pulse indicates when the second rollover occurred, but it gives no information of what the actual time was or is. Thus, the timing signal is typically accompanied with a serial message defining the time of day, day of year and other parameters. With this additional information, the timing signal can be used in precise timing applications.
In a typical timing application, the GNSS receiver will be configured to dispatch the timing and serial signal for synchronisation, as shown in FIG. 1. The customer will normally want to clock the whole system from a single clock source, for example the reference or system clock. This usually presents no problems, as long as the timing signal itself is generated directly from the reference clock.
However, in some receivers, the timing signal is not generated directly from the reference clock REF_CLK, but rather from an internal clock CLK2 as shown in FIG. 1. This internal clock CLK2 may not be running at the same frequency as the reference clock REF_CLK. For example, the reference clock might be 26 MHz, whereas the internal clock might be 48 MHz. Consequently, the timing signal is not synchronous to the reference clock, and this can present several problems, including the following:                The time at which the timing signal is used by the customer will be the next 26 MHz edge after the timing signal arises. This effectively adds a 26 MHz saw-tooth error to the timing signal;        The input of the system clocked off the 26 MHz reference clock REF_CLK may measure the timing signal as a metastable event, since the edge is not synchronous to its clock. Correcting for this may take several clock cycles, and hence an even larger timing error. Further, if the timing pulse is short, then this may prevent it from being observed at all.        The system will often require an exact number of clock cycles between the timing events (26,000,000 of them for a 26 MHz case using a PPS signal). If the timing signal is not synchronous to the 26 MHz clock, then this can't be guaranteed.        